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(R)
L6384
HIGH-VOLTAGE HALF BRIDGE DRIVER
HIGH VOLTAGE RAIL UP TO 600 V dV/dt IMMUNITY +- 50 V/nsec IN FULL TEMPERATURE RANGE DRIVER CURRENT CAPABILITY: 400 mA SOURCE, 650 mA SINK SWITCHING TIMES 50/30 nsec RISE/FALL WITH 1nF LOAD CMOS/TTL SCHMITT TRIGGER INPUTS WITH HYSTERESIS AND PULL DOWN SHUT DOWN INPUT DEAD TIME SETTING UNDER VOLTAGE LOCK OUT INTEGRATED BOOTSTRAP DIODE CLAMPING ON Vcc SO8/MINIDIP PACKAGES DESCRIPTION The L6384 is an high-voltage device, manufactured with the BCD"OFF-LINE" technology. It has BLOCK DIAGRAM
SO8
Minidip
ORDERING NUMBERS: L6384D L6384
an Half - Bridge Driver structure that enables to drive N Channel Power MOS or IGBT. The Upper (Floating) Section is enabled to work with voltage Rail up to 600V. The Logic Inputs are CMOS/TTL compatible for ease of interfacing with controlling devices. Matched delays between Lower and Upper Section simplify high frequency operation. Dead time setting can be readily accomplished by means of an external resistor.
H.V. VCC 2 8 BOOTSTRAP DRIVER UV DETECTION R IN 1 VCC Idt DT/SD 3 Vthi
D97IN518A
VBOOT
HVG DRIVER S 7
CBOOT HVG
LOGIC LEVEL SHIFTER DEAD TIME VCC
OUT 6
LOAD
5 LVG DRIVER
LVG
4
GND
May 2000
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L6384
ABSOLUTE MAXIMUM RATINGS
Symbol Vout Vcc Is Vboot Vhvg Vlvg Vi Vsd dVout/dt Ptot Tj Ts Output Voltage Supply Voltage (*) Supply Current (*) Floating Supply Voltage Upper Gate Output Voltage Lower Gate Output Voltage Logic Input Voltage Shut Down/Dead Time Voltage Allowed Output Slew Rate Total Power Dissipation (Tj = 85 C) Junction Temperature Storage Temperature Parameter Value -3 to Vboot -18 - 0.3 to 14.6 25 -1 to 618 -1 to Vboot -0.3 to Vcc +0.3 -0.3 to Vcc +0.3 -0.3 to Vcc +0.3 50 750 150 -50 to 150 Unit V V mA V V V V V V/ns mW C C
(*) The device has an internal Clamping Zener between GND and the Vcc pin, It must not be supplied by a Low Impedence Voltage Source. Note: ESD immunity for pins 6, 7 and 8 is guaranteed up to 900 V (Human Body Model)
PIN CONNECTION
IN VCC DT/SD GND
1 2 3 4
D97IN519
8 7 6 5
VBOOT HVG VOUT LVG
THERMAL DATA
Symbol Rth j-amb Parameter Thermal Resistance Junction to Ambient SO8 150 Minidip 100 Unit C/W
PIN DESCRIPTION
N. 1 2 3 Name IN Vcc DT/SD Type I I I Function Logic Input: it is in phase with HVG and in opposition of phase with LGV. It is compatible to VCC voltage. [Vil Max = 1.5V, Vih Min = 3.6V] Supply input voltage: there is an internal clamp [Typ. 15.6V] High impedance pin with two functionalities. When pulled lower than Vdt [Typ. 0.5V] the device is shut down. A voltage higher than Vdt sets the dead time between high side gate driver and low side gate driver. The dead time value can be set forcing a certain voltage level on the pin or connecting a resistor between pin 3 and ground. Care must be taken to avoid below threshold spikes on pin 3 that can cause undesired shut down of the IC. For this reason the connection of the components between pin 3 and ground has to be as short as possible. This pin can not be left floating for the same reason. The pin has not be pulled through a low impedance to VCC, because of the drop on the current source that feeds Rdt. The operative range is: Vdt....270K Idt, that allows a dt range of 0.4 - 3.1s. Ground
4
GND
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L6384
PIN DESCRIPTION (continued)
N. 5 Name LVG Type O Function Low Side Driver Output: the output stage can deliver 400mA source and 650mA sink [Typ. Values]. The circuit guarantees 0.3V max on the pin (@ Isink = 10mA) with VCC > 3V and lower than the turn on threshold. This allows to omit the bleeder resistor connected between the gate and the source of the external mosfet normally used to hold the pin low; the gate driver ensures low impedance also in SD conditions. Upper Driver Floating Reference: layout care has to be taken to avoid below ground spikes on this pin. High Side Driver Output: the output stage can deliver 400mA source and 650mA sink [Typ. Values]. The circuit gurantees 0.3V max between this pin and Vout (@ Isink = 10mA) with VCC > 3V and lower than the turn on threshold. This allows to omit the bleeder resistor connected between the gate and the source of the external mosfet normally used to hold the pin low; the gate driver ensures low impedance also in SD conditions. Bootstrap Supply Voltage: it is the upper driver floating supply. The bootstrap capacitor connected between this pin and pin 6 can be fed by an internal structure named "bootstrap driver" (a patented structure). This structure can replace the external bootstrap diode.
6 7
Vout HVG
O O
8
Vboot
RECOMMENDED OPERATING CONDITIONS
Symbol Vout Vboot Vout fsw Vcc Tj 2 Pin 6 8 Parameter Output Voltage Floating Supply Voltage Switching Frequency Supply Voltage Junction Temperature -45 HVG,LVG load CL = 1nF Test Condition Min. Note1 Note1 Typ. Max. 580 17 400 Vclamp 125 Unit V V kHz V C
Note 1: If the condition Vboot - Vout < 18V is guaranteed, Vout can range from -3 to 580V.
ELECTRICAL CHARACTERISTICS AC Operation (VCC = 14.4V; Tj = 25C)
Symbol ton tonsd toff Pin 1 vs 5,7 3 vs 5,7 1 vs 5,7 Parameter High/Low Side Driver Turn-On Propagation Delay Shut Down Input Propagation Delay High/Low Side Driver Turn-Off Propagation Delay Vout = 0V R dt = 47k Vout = 0V R dt = 146k Vout = 0V R dt = 270k tr tf 7,5 7,5 Rise Time Fall Time CL = 1000pF CL = 1000pF Test Condition Vout = 0V R dt = 47k Min. Typ. 200+dt 220 250 200 170 70 30 280 300 250 200 Max. Unit ns ns ns ns ns ns ns
DC Operation (VCC = 14.4V; Tj = 25C)
Supply Voltage Section Vclamp Vccth1 Vccth2 2 2 2 Supply Voltage Clamping Vcc UV Turn On Threshold Vcc UV Turn Off Threshold Is = 5mA 14.6 11.5 9.5 15.6 12 10 16.6 12.5 10.5 V V V 3/10
L6384
DC Operation (continued)
Symbol Vcchys Iqccu Iqcc Vboot IQBS ILK Rdson Iso Isi Logic Inputs Vil Vih Iih Iil Iref dt 3 3 vs 5,7 3 2,3 Low Level Logic Threshold Voltage High Level Logic Threshold Voltage High Level Logic Input Current Low Level Logic Input Current Dead Time Setting Current Dead Time Setting Range (**) Rdt = 47k Rdt = 146 Rdt = 270k 0.4 VIN = 15V VIN = 0V 28 0.5 1.5 2.7 0.5
(VCC - VCBOOT1) - (VCC - VCBOOT2) I1(VCC,VCBOOT1) - I2(VCC,VCBOOT2)
Pin 2 2 2 8
Parameter Vcc UV Hysteresis Undervoltage Quiescent Supply Current Quiescent Current Bootstrap Supply Voltage Quiescent Current High Voltage Leakage Current Bootstrap Driver on Resistance (*)
Test Condition Vcc 11V Vin = 0
Min.
Typ. 2 150 380
Max.
Unit V A
500 17
A V A A mA mA
Bootstrapped supply Voltage Section Vout = Vboot; IN = HIGH VHVG = Vout = Vboot = 600V Vcc 12.5V; IN = LOW VIN = Vih (tp < 10s) VIN = Vil (tp < 10s) 300 500 125 400 650 1.5 3.6 50 70 1 200 10
High/Low Side Driver 5,7 Source Short Circuit Current Sink Short Circuit Current
V V A A A s s s V
3.1
Vdt
Shutdown Threshold
(*) RDSON is tested in the following way: RDSON =
where I1 is pin 8 current when VCBOOT = VCBOOT1, I2 when VCBOOT = VCBOOT2 (**) Pin 3 is a high impedence pin. Therefore dt can be set also forcing a certain voltage V3 on this pin. The dead time is the same obtained with a Rdt if it is: Rdt Iref = V3.
Figure 1. Input/Output Timing Diagram
IN SD
HVG LVG
D99IN1017
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L6384
Figure 2. Typical Rise and Fall Times vs. Load Capacitance
time (nsec) 250 200 Tr 150 Tf 100 50 0
D99IN1015
Figure 3. Quiescent Current vs. Supply Voltage
Iq (A) 104
D99IN1016
103
102
10
0 1 2 3 4 5 C (nF) For both high and low side buffers @25C Tamb
0
2
4
6
8
10
12
14
VS(V)
BOOTSTRAP DRIVER A bootstrap circuitry is needed to supply the high voltage section. This function is normally accomplished by a high voltage fast recovery diode (fig. 4a). In the L6384 a patented integrated structure replaces the external diode. It is realized by a high voltage DMOS, driven synchronously with the low side driver (LVG), with in series a diode, as shown in fig. 4b An internal charge pump (fig. 4b) provides the DMOS driving voltage . The diode connected in series to the DMOS has been added to avoid undesirable turn on of it. CBOOT selection and charging: To choose the proper CBOOT value the external MOS can be seen as an equivalent capacitor. This capacitor CEXT is related to the MOS total gate charge : Qgate CEXT = Vgate The ratio between the capacitors CEXT and CBOOT is proportional to the cyclical voltage loss . It has to be: CBOOT>>>CEXT e.g.: if Qgate is 30nC and Vgate is 10V, CEXT is 3nF. With CBOOT = 100nF the drop would be 300mV. If HVG has to be supplied for a long time, the CBOOT selection has to take into account also the leakage losses. e.g.: HVG steady state consumption is lower than 200A, so if HVG TON is 5ms, CBOOT has to supply 1C to CEXT. This charge on a 1F ca-
pacitor means a voltage drop of 1V. The internal bootstrap driver gives great advantages: the external fast recovery diode can be avoided (it usually has great leakage current). This structure can work only if VOUT is close to GND (or lower) and in the meanwhile the LVG is on. The charging time (Tcharge ) of the CBOOT is the time in which both conditions are fulfilled and it has to be long enough to charge the capacitor. The bootstrap driver introduces a voltage drop due to the DMOS RDSON (typical value: 125 Ohm). At low frequency this drop can be neglected. Anyway increasing the frequency it must be taken in to account. The following equation is useful to compute the drop on the bootstrap DMOS: Vdrop = IchargeRdson Vdrop = Qgate Rdson Tcharge
where Qgate is the gate charge of the external power MOS, Rdson is the on resistance of the bootstrap DMOS, and Tcharge is the charging time of the bootstrap capacitor. For example: using a power MOS with a total gate charge of 30nC the drop on the bootstrap DMOS is about 1V, if the Tcharge is 5s. In fact: Vdrop = 30nC 125 ~ 0.8V 5s
Vdrop has to be taken into account when the voltage drop on CBOOT is calculated: if this drop is too high, or the circuit topology doesn't allow a sufficient charging time, an external diode can be used.
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L6384
Figure 4. Bootstrap Driver
DBOOT
VS
VBOOT H.V. HVG CBOOT VOUT TO LOAD LVG
VS
V BOOT H.V. HVG CBOOT V OUT TO LOAD LVG
a
b
D99IN1067
Figure 5. Dead Time vs. Resistance.
3.5
Figure 7. Driver Propagation Delay vs. Temperature.
400
@ Vcc = 14.4V
3.0 2.5
@ Vcc = 14.4V
300 Ton,Toff(ns)
Typ.
2.0
Typ.
@ Rdt = 47kOhm
dt (s)
1.5 1.0 0.5 0.0 50 100 150 200 250 300
200
Typ. Typ.
100
@ Rdt = 270kOhm @ Rdt = 146kOhm
0 -45 -25 0 25 50 Tj (C) 75 100 125
Rdt (kOhm)
Figure 6. Dead Time vs. Temperature.
3 2.5 2 dt (us) 1.5
Typ. Typ.
Figure 8. Shutdown Threshold vs. Temperature
1
R=270K
0.8
@ Vcc = 14.4V
@ Vcc = 14.4V
Vdt (V) 0.6 0.4 0.2
Typ.
R=146K
Typ.
1 0.5 R=47K -25 0 25 50 Tj (C) 75 100 125 0 -45
0 -45 -25 0 25 50 Tj (C) 75 100 125
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L6384
Figure 9. Vcc UV Turn On vs. Temperature
15 14 Vccth1 (V)
Figure 11. Output Source Current vs. Temperature.
1000 800 Current (mA)
13 12 11 10 -45 -25 0 25 50 Tj (C) 75 100 125
Typ.
@ Vcc = 14.4V
600
Typ.
400 200 0 -45
-25
0
25 50 Tj (C)
75
100
125
Figure 10. Vcc UV Turn Off vs. Temperature
13
Figure 12. Output Sink Current vs.Temperature
1000 12 800 Vccth2 (V) Current (mA) 11 10 9 8 -45 -25 0 25 50 Tj (C) 75 100 125 0 -45 -25 0 25 50 Tj (C) 75 100 125
Typ.
Typ.
@ Vcc = 14.4V
600 400 200
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L6384
DIM. MIN. A a1 B b b1 D E e e3 e4 F I L Z 3.18 7.95 0.51 1.15 0.356 0.204
mm TYP. 3.32 0.020 1.65 0.55 0.304 10.92 9.75 2.54 7.62 7.62 6.6 5.08 3.81 1.52 0.125 0.313 0.045 0.014 0.008 MAX. MIN.
inch TYP. 0.131 MAX.
OUTLINE AND MECHANICAL DATA
0.065 0.022 0.012 0.430 0.384 0.100 0.300 0.300 0.260 0.200 0.150 0.060
Minidip
8/10
L6384
DIM. MIN. A a1 a2 a3 b b1 C c1 D (1) E e e3 F (1) L M S 3.8 0.4 4.8 5.8 0.65 0.35 0.19 0.25 0.1
mm TYP. MAX. 1.75 0.25 1.65 0.85 0.48 0.25 0.5 0.026 0.014 0.007 0.010 0.004 MIN.
inch TYP. MAX. 0.069 0.010 0.065 0.033 0.019 0.010 0.020
OUTLINE AND MECHANICAL DATA
45 (typ.) 5.0 6.2 1.27 3.81 4.0 1.27 0.6 8 (max.) 0.15 0.016 0.189 0.228 0.050 0.150 0.157 0.050 0.024 0.197 0.244
SO8
(1) D and F do not include mold flash or protrusions. Mold flash or potrusions shall not exceed 0.15mm (.006inch).
9/10
L6384
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 2000 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com
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